1. Technical Field
A conventional voltage regulator is described. FIG. 6 is a circuit diagram illustrating the conventional voltage regulator.
2. Background Art
In general, an output section of a voltage regulator is connected to a capacitor in order to stabilize its regulating operation and improve its transient response characteristics. Also in this example, a load capacitor 95 is connected. A power supply unit 91 outputs a power supply voltage VDD. Based on the power supply voltage VDD, a voltage regulator 92 outputs an output voltage Vout which is a constant voltage. Based on the power supply voltage VDD, a voltage detection circuit 93 controls ON/OFF of an NMOS transistor 94.
If the power supply unit 91 shuts down, the power supply voltage VDD decreases, and the output voltage Vout decreases as well. When the power supply voltage VDD decreases to be lower than a predetermined voltage, the voltage detection circuit 93 controls the NMOS transistor 94 so that the NMOS transistor 94 may be turned ON, and then the NMOS transistor 94 is turned ON. Then, an output terminal of the voltage regulator 92 and a ground terminal is connected with each other, and hence the load capacitor 95 is forcedly discharged so that the output voltage Vout may decrease owing also to the NMOS transistor 94. In this case, the load capacitor 95 is discharged more rapidly with the NMOS transistor 94 than without the NMOS transistor 94 (see, for example, Patent Document 1).
Patent Document 1: JP 2000-152497 A